1. Field of the Invention
The present invention relates to the field of integrated circuit design. More specifically, the invention relates to circuits for generating clocking signals within computers and other electronic systems.
2. Description of Related Art
Electronic systems utilize various types of clocking signals to provide required timing functions. Generally, an integrated circuit (IC) is provided with an external clocking signal from which multiple internal clocking signals for the IC are derived. However, the external clocking signal often does not have a well-defined duty cycle. It therefore becomes necessary to provide internal clocking signals at the same frequency as the external clock which are not dependent upon the duty cycle of the external clock. Circuits which perform this function typically consist of closed-loop solutions such as phase-locked loops (PLL), delay-locked loops (DLL) or synchronous delay loops (SDL).
FIG. 1 provides a block diagram of a representative PLL circuit. The PLL uses a phase/frequency detector (PFD) 102 to measure the error in phase/frequency between the input signal EXT CLK and the generated output signal INT CLK. The PFD 102 generates pulses on either a LEAD or LAG output, depending on the relative phase difference between EXT CLK and INT CLK, causing the charge pumps 104 to either charge or discharge, respectively. The output of charge pumps 104 is then passed through a low pass filter 106 and provided as the control voltage VCNTL for a voltage controlled oscillator (VCO) 108. The control voltage VCNTL causes VCO 108 to adjust its output frequency until there is no phase/frequency error between EXT CLK and INT CLK. In steady-state, the generated output INT CLK will be locked to the phase of the input EXT CLK.
The closed-loop solutions may pose a design problem, however, when used in certain applications where power consumption is critical, such as in laptop computers or cellular telephones. In order to reduce power consumption, these applications often employ "power down" techniques, which include temporarily "powering down" or disabling individual subcircuits within a system when they are not in use, lowering the external clock frequency or, in cases of prolonged inactivity, stopping the external clock completely. Unfortunately, PLL, DLL and SDL circuits do not provide instantaneous recovery once the external clock is re-established or its frequency restabilized. These circuits typically require between 500 and 1500 external clock cycles to become resynchronized to the external clock. During this "lock-in" time, these closed-loop circuits commonly generate spurious signals and glitches, leading to unpredictable results from any circuitry which receives clocking signals from these circuits.
The long lock-in time associated with closed-loop clocking circuits is the result of a design trade-off between circuit stability and lock-in time. Specifically, lock-in time may be improved (reduced) by increasing the bandwidth of the closed-loop system. Referring again to FIG. 1, the system bandwidth of the PLL can be adjusted by appropriately selecting the gains of phase/frequency detector 102, low pass filter 106 and VCO 108. However, reducing the lock-in time by merely a factor of two can introduce unacceptable jitter into the circuit at steady-state. It is desirable, therefore, to provide a circuit for generating internal clocking signals at the external clock frequency which is capable of resuming normal operation immediately following a power down state, a stopping of the external clock, or a change in the external clock frequency.
In addition, it is often necessary to provide multiple internal clocking signals at a given frequency with non-overlapping phases. Two active high clocking signals have overlapping phases if there exists an overlapping interval, t.sub.OL, during which both signals are high. Accordingly, two active high clocking signals which are never high simultaneously have non-overlapping phases. For signals with non-overlapping phases, the non-overlapping interval, t.sub.NOL, is defined as the delay from the trailing edge of one signal to the rising edge of the other. There are numerous advantages to providing two clocking signals having a single frequency and non-overlapping phases, such as the avoidance of contention in precharge circuits or the ensuring of correct propagation of data through successive latch stages.
Thus, what is desired is a circuit for generating, in response to an external clock, two clocking signals having a single frequency and non-overlapping phases, where the circuit is independent of the external clock duty cycle and is capable of immediate recovery after power management states.